1. Field of the Invention
Embodiments of the present invention relate to a ferroelectric random access memory device and a method of driving the same.
2. Description of the Related Art
A ferroelectric random access memory device (Ferroelectric Random Access Memory; FRAM, FeRAM) that uses a ferroelectric thin film is a type of ferroelectric random access memory device, and it is non-volatile device, in that it can store information in a condition where power is not supplied to the device. In addition, FRAM devices can support high-speed access and have low power consumption and strong shock resistance. Accordingly, FRAMs can be used as a storage medium for various electronic apparatuses, such as portable computers, cellular telephones, and gaming machine, which can store and search files.
The ferroelectric random access memory device includes ferroelectric memory cells, each cell being composed of a ferroelectric capacitor and an access transistor. Each cell stores logical data, for example, “1” or “0” binary data, according to the electrical polarization state of the ferroelectric capacitor. When a voltage is applied to both ends of the ferroelectric capacitor, the ferroelectric thin film is polarized according to the direction of the electric field.
FIG. 1 is a timing chart illustrating the signals involved in a read operation of a conventional ferroelectric random access memory device.
First, signals will be described with reference to FIG. 1. A chip enable signal CEB represents whether a chip is enabled/disabled. A plate line control signal PPLS is used to control a plate line that is connected to one end of the ferroelectric capacitor. A sense amplifier enable signal SAEN is used to enable a sense amplifier circuit that is coupled to a ferroelectric memory cell to be read.
A read operation of the ferroelectric random access memory device typically includes a charge-sharing operation, a sensing operation, and a write-back operation.
The charge-sharing operation is performed during a charge-sharing period t1. During the charge-sharing period t1, the plate line control signal PPLS is enabled, and the sense amplifier enable signal SAEN is disabled. The sensing operation is performed during a sensing period t2. During the sensing period t2, the plate line control signal PPLS is enabled, and the sense amplifier enable signal SAEN is enabled. The write-back operation is performed during a write-back period t3. During the write-back period t3, the plate line control signal PPLS is disabled, and the sense amplifier enable signal SAEN is enabled.
During the charge-sharing period t1, a voltage corresponding to data stored in the ferroelectric capacitor is transferred to a bit line BL. During the sensing period t2, the sense amplifier senses and amplifies data that is on the bit line BL. During the write-back period t3, the original data that is stored in the ferroelectric memory cell is written back following the sensing operation. The write-back period t3 is needed because the ferroelectric random access memory device reads data using a process that is referred to as a “destructive read”. Here, the destructive read means that when data is read from a memory cell where “1” is stored, the data stored in the memory cell is temporarily changed (that is, data “0” is stored) during the read operation. Accordingly, to prevent stored data from becoming permanently changed after the read operation, original data needs to be written back in the write-back operation following the sensing operation.